1. Field of the Invention
The present invention relates to a differential amplifier using MOS transistors.
2. Discussion of Related Art
Differential amplifiers are used in many integrated circuits. The present invention is concerned more particularly with amplifiers that have only one stage, having high gain like those used especially in circuits for reading non-volatile memories. For this type of application, it is common practice to use differential amplifiers with asymmetrical outputs. The active load used to this end by these differential amplifiers is a current mirror structure.
While these differential amplifiers with asymmetrical outputs are widely used, it has been observed, however, that they do not work very well at an excessively low logic supply voltage VCC. Indeed, it is known that technological efforts are being made particularly to reduce the level of the logic supply voltage of the integrated circuits. It has been sought in particular to make these circuits work at 2 volts or even 1 volt. Now, with a current mirror assembly, there is a transistor mounted as a diode. This leads to a systematic drop in a transistor voltage threshold, of about 0.8 volts for a P type transistor. With a logic supply voltage VCC of 2 volts, this amounts to a drop in voltage by nearly half. It will be understood therefore that this voltage drop inherent in the structure of this amplifier is a real factor of limitation at low VCC.
It is an object of the present invention to resolve this technical problem of limitation at low VCC, while maintaining high gain.
For a clearer understanding of the nature of the technical problem to be resolved, FIG. 1 shows a drawing of a known differential amplifier using MOS transistors. This differential amplifier is used especially in non-volatile memory read circuits to compare the voltage on a bit line with a reference voltage. Even if not specifically mentioned, all of the transistors in the following description of the preferred embodiment are metal-oxide semiconductor (MOS) transistors.
The differential amplifier has a first arm (also called a branch) and a second arm that are parallel-connected on the one hand to a first supply voltage and on the other hand to a bias transistor M5. This bias transistor M5 is connected to a second supply voltage and receives a bias potential at its gate. Each arm has a load transistor M1 or M2 and an amplifier transistor M3 or M4 that are series-connected. The load transistors are mounted as a current mirror. The transistor M1 is mounted as a diode (with the gate and drain connected). The point of connection between the load transistor M1 and the amplifier transistor M3 is referenced A, and is at the potential VA. The point of connection between the load transistor M2 and the amplifier transistor M4 is the output OUT of the amplifier. The two inputs, namely the positive input E1 and the negative input E2, of this differential amplifier with asymmetrical outputs are formed respectively by the gate of the transistor M3 and the gate of the transistor M4. The two voltages to be compared are applied to them, these voltages being conventionally referenced V.sub.+ for E1 and V.sub.- for E2.
The example has been described in the context of CMOS technology. The MOS transistor M1 is thus a P type transistor and is connected as a forward-biased diode with its gate connected to its drain. Its source is connected to the supply voltage VCC. Its drain is connected to the drain of the MOS transistor M3 which is an N type transistor. The MOS load transistor M2 too is a P type transistor and its gate is connected to the gate of the transistor M1 (mounted as a diode). Its source is connected to the voltage VCC. Its drain is connected to the drain of the N type transistor M4.
The sources of the transistors M3 and M4 are connected together, at a point referenced S, to the drain of the N type current bias transistor M5.
In the example, the amplifier transistors M3 and M4 are native transistors, namely they have a very low threshold voltage V.sub.tw, which is represented by an additional stroke in the drawing.
In the exemplary use of this amplifier in a read circuit for a memory, one of the inputs of the comparator, in the example the input E1, has the voltage BL of a bit line of the memory (the bit line that is being read) and the other input, in the example E2, has the reference read voltage VREF. In an application of this kind, the inputs BL and VREF have a maximum voltage level of 1 volt.
The ideal operation of a comparator of this kind follows the characteristic curve defined as follows:
IF V.sub.+ -V.sub.- &gt;0 THEN VOUT=VCC AND PA1 IF V.sub.+ -V.sub.- &lt;0 THEN VOUT=GND. PA1 IF V.sub.+ -V.sub.- &gt;.epsilon. THEN VOUT=VCC AND PA1 IF V.sub.+ -V.sub.- &lt;-.epsilon. THEN VOUT=GND PA1 IF -.epsilon.&lt;V.sub.+ -V.sub.- &lt;+.epsilon. PA1 THEN VOUT=K(V.sub.+ -V.sub.-)+VCC/2. PA1 g.sub.Mi is the gain of the transistor Mi in saturated mode (g.sub.+Mi =m.sub.0 C.sub.OX W/2L); PA1 V.sub.tn is the threshold voltage of an N type MOS transistor (M5); PA1 V.sub.tw is the threshold voltage of a native N type MOS transistor (M3 or M4); PA1 V.sub.tp is the threshold voltage of a P type MOS transistor (M1, M2); PA1 VDF is the differential input voltage equal to (V.sub.+ -V.sub.-)/2; PA1 K is the gain in differential mode, equal to .DELTA.V.sub.OUT /.DELTA.V.sub.DF ; PA1 G.sub.mi is the small-signal transconductance for the transistor Mi, equal to .delta.I.sub.DS /.epsilon.V.sub.GS ; and PA1 r.sub.0Mi is the drain saturation resistance of the transistor Mi due to the modulation of the width of the channel.
This ideal characteristic has an infinite gain when V.sub.+ =V.sub.-.
Under real conditions of operation, there is a high gain in the region of V.sub.+ =V.sub.-. If this gain is referenced K, the corresponding curve is the one shown in FIG. 2, defined as follows:
In order that this function may be continuous, we must have the following as relationships: EQU K*.epsilon.=VCC/2, that is (1) EQU 2*.epsilon.=VCC/K. (2)
These relationships (1) or (2) clearly show that the higher the gain, the narrower is the critical zone between -.epsilon. and +.epsilon. where the output voltage VOUT is neither VCC nor GND the higher the gain, the closer we come to ideal characteristic curve.
It is therefore very important to have optimum gain, namely the greatest possible gain. This is why all the transistors M1 to M4 of the amplifier must work in saturated mode, especially in the critical zone [-.epsilon.; +.epsilon.].
Hereinafter, it will be shown that this condition can be achieved in the prior art circuit only for a supply voltage of over 2 volts, on the basis of the typical values in a given CMOS technology.
The zone with which the present invention is concerned more particularly is the critical zone [-.epsilon.; +.epsilon.], corresponding to the switching-over of the output VOUT of the amplifier. It is at this point in time that the greatest possible gain is needed.
In the following computations, it is assumed that V.sub.+ =V.sub.-, with transistors M1 to M5 in saturated mode. The transistors M1 and M2 are identical and the transistors M3 and M4 are identical.
At a first stage, a computation will be made of the value of the small-signal gain in differential mode K of an amplifier of this kind, assuming that V.sub.+ =V.sub.- and assuming that around this point .DELTA.V.sub.+ =-.DELTA.V.sub.-
It is assumed that VS is constant. Furthermore, the following notational conventions are adopted:
The current variation in the arm (M1, M3) is: .DELTA.I.sub.M3 =G.sub.M3 *.DELTA.V.sub.+.
Since this current flows in the arm (M2, M4) through the current mirror formed by the transistors M1 and M2, the current variation in this arm is: .DELTA.I.sub.M2 =.DELTA.I.sub.M3 =G.sub.M3 *.DELTA.V.sub.+.
Since G.sub.M3 =G.sub.M4 (identical transistors) and .DELTA.V.sub.+ =-.DELTA.V.sub.- (differential mode), we have: EQU .DELTA.I.sub.M2 =-.DELTA.I.sub.M4.
The output current is: EQU .DELTA.I.sub.M2 -.DELTA.I.sub.M4 =2.DELTA.I.sub.M2 =2.DELTA.I.sub.M3 =2G.sub.M3 .DELTA.V.sub.+ =2G.sub.M4 .DELTA.V.sub.+.
This current flows into the equivalent output resistor (in small signals) corresponding to the saturation resistance r.sub.0M2 of the transistor M2 in parallel with the saturation resistance r.sub.0M4 of the transistor M4. The variation in the output voltage is therefore: EQU .DELTA.VOUT=2G.sub.M4 .DELTA.V.sub.+ (r.sub.0M2 //r.sub.0M4).
With .DELTA.VDF=(.DELTA.V.sub.+ -.DELTA.V.sub.-)/2=.DELTA.V.sub.+, the value of the gain in differential mode is deduced therefrom: EQU K=.DELTA.VOUT/.DELTA.VDF=2G.sub.M4 .DELTA.V.sub.+ (r.sub.0M2 //r.sub.0M4).
A search shall now be made for the condition, with the respect to the supply voltage VCC, that enables the transistors to be really in saturation mode.
The current I3 flowing into the transistor M3 and the current I4 flowing into the transistor M4 are equal and given by the following relationship in saturated mode: EQU I3=I4=g.sub.M3 (V.sub.+ -V.sub.- -V.sub.tw).sup.2. (a)
If the transistor M3 is saturated, we also have the following relationship (b): EQU V.sub.A &gt;V.sub.+ -V.sub.tw. (b)
The current I1 in the transistor M1 and the current I2 in the transistor M2 are equal and given by the following relationship (c): EQU I1=I2=g.sub.M1 (VCC-VA-V.sub.tp).sup.2. (c)
Since the transistors M1 and M2 are series-connected, we have I1=I3, and therefore: EQU g.sub.M1 (VCC-VA-V.sub.tp).sup.2 =g.sub.M3 (V.sub.+ -V.sub.- -V.sub.tw).sup.2. (d)
If we write y=(g.sub.M3 /g.sub.M1), we therefore have: EQU VA=VCC-V.sub.tp -y(V.sub.+ -VS-V.sub.tw). (e)
In the relationship (b) of saturation of the transistor M3, we get: EQU VCC-V.sub.tp -y(V.sub.+ -VS-V.sub.tw)&gt;V.sub.+ -V.sub.tw.
It is therefore necessary, in order to fulfil the saturation condition, that the supply voltage VCC should be such that: EQU VCC&gt;(y+1)(V.sub.+ -V.sub.tw)+V.sub.tp -yVS.
With the following typical values: V.sub.tp =0.8 volt; y=1; V.sub.tw =0.4 volt; VS=0.2 volt and for an application of the memory read circuit type, in which there will be V.sub.+ =1 volt, it is therefore necessary that VCC&gt;1.8 volts to ensure the saturation condition of the transistors.
In practice, for circuits supplied with VCC equal to 2 volts in nominal voltage, the working of the circuit must be guaranteed up to at least 1.6 volts. It can be seen that the condition of saturation is no longer fulfilled at this value. It is therefore not possible to contemplate the use of this circuit at less than VCC=3 volts.
To ensure the condition of saturation at a lower VCC, the value of the ratio y between the gains of the transistors M1 and M3 could be reduced. However, for VCC=1.6 volts, we must have y=0.25. In practice, this means that the P type transistor M1 should have eight times the gain of the N type native transistor M3. Since in addition the gain per unit of width of a P type transistor is equal to half that of a native transistor, this means that in fact there should be a size ratio of 16 to 1 between the P type transistor M1 and the native transistor M3. A transistor M1 of such a large size imposes major constraints of design and increases the parasitic charges. This implies a reduction in switching speed. This approach therefore is not acceptable.
Another way to succeed in obtaining this inequality is to change the technology, so as to have transistor threshold voltages (V.sub.tw and V.sub.tp) that are even lower. This approach is not valuable because, if the threshold voltages are reduced, the sub-threshold leakage currents are necessarily increased. This is particularly troublesome for so-called portable applications, using battery-powered integrated circuits.
In the present invention, another way has been sought to ensure the condition of saturation, even at low logic supply voltage VCC, while at the same time keeping the gain of this amplifier.